1. Field of the Invention
The present invention relates to a memory card used with a host system, such as an information processing device, connected thereto.
2. Description of the Related Art
In general, a memory card is used while being connected to a host system which processes information. The memory card is connected to the host system such that the host system can store, read, or overwrite data in the memory card. For such a memory card, for example, a flash memory is used. Only when the host system checks a device ID stored in the memory card and determines that the memory card is compatible with the host system, the host system can read, write, or delete data in the memory card.
FIG. 3 is a block diagram illustrating a first exemplary configuration of a conventional memory card. In FIG. 3, a memory card 101 includes a component memory section 102 in which data can be overwritten, and a card control section 103 which includes a bus buffer, an address decoder, etc.
The component memory section 102 includes a command control-type memory section for storing a device ID. The device ID includes a manufacturer code (e.g., a code assigned to Sharp K.K. is B0H) and a device code (e.g., a code assigned to a 16Mb device is D0H, where every product type of device has its own device code).
The card control section 103 controls the component memory section 102 by using the address decoder, etc. A host system 100 outputs an address signal and a command signal to the memory card 101 through an address bus AB and a data bus DB, respectively. Based on these signals, the host system 100 writes data to a prescribed address in the component memory section 102 or reads data corresponding to a prescribed address from the component memory section 102.
When a reset signal RESET is input to the card control section 103, the card control section 103 outputs a reset signal RESETxe2x80x2 to the component memory section 102 to put the component memory section 102 into a reset state. Note that there are generally two types of memory cards. A memory card of the first type is put into a reset state by a high-level signal. A memory card of the second type is put into a reset state by a low-level signal. In this conventional example, the memory card is put into a reset state by a high-level signal.
When a write enable signal WE# which is a write selection signal, a chip enable signal CE# which is a chip selection signal, and an output enable signal OE# which is a data output selection signal are input from the host system 100 to the card control section 103, the card control section 103 outputs a write enable signal WE#xe2x80x2, a chip enable signal CE#xe2x80x2, and an output enable signal OE#xe2x80x2, respectively, to the component memory section 102. The symbol xe2x80x9c#xe2x80x9d indicates the inversion of a signal level, which means that a signal is active when low. This allows the component memory section 102 to be put into an active state by a low-level signal. The card control section 103 outputs the address signal and the command signal from the host system 100 to the component memory section 102 through the address bus AB and the data buses DB, DBxe2x80x2, respectively. Based on these signals, the card control section 103 controls reading or writing of data corresponding to an address in the component memory section 102 which is designated by the address signal. In the case where data can be written in the component memory section 102, the write enable signal WE# is at a low level.
In the above described configuration, the host system 100 reads a device ID from the memory card 101 to check the device ID and to determine whether or not the memory card 101 is compatible with the host system 100 in the manner described below.
When the component memory section 102 is in a state such that data can be read therefrom (xe2x80x9cread array modexe2x80x9d), the chip enable signal CE#, the write enable signal WE#, and the output enable signal OE#, which are output from the host system 100, are set to an active state (low level), an active state (low level), and an inactive state (high level), respectively.
Next, the host system 100 outputs an ID transmission request command, for example, 9090H, to the card control section 103 through the data bus DB, and then the card control section 103 outputs the ID transmission request command 9090H to the component memory section 102 through the data bus DBxe2x80x2.
The component memory section 102 recognizes the ID transmission request command 9090H output from the card control section 103, and outputs the device ID stored in the component memory section 102 to the card control section 103 through the data bus DBxe2x80x2. The card control section 103 outputs the device ID received from the component memory section 102 to the host system 100 through the data bus DB.
The host system 100 checks the device ID output from the memory card 101 to determine whether or not the memory card 101 is compatible with the host system 100. If the memory card 101 is determined to be compatible with the host system 100, operations such as reading or writing of data can be performed between the memory card 101 and the host system 100 according to command signals output from the host system 100. If the host system 100 determines otherwise, operations cannot be performed between the memory card 101 and the host system 100 according to command signals output from the host system 100.
The command signal is not limited to the ID transmission request command 9090H described above. A flash memory card which is available from Sharp K.K. accepts a reset command FFFFH, a status register read command 7070H, a status register clear command 5050H, a deletion command D0D0H, a write set-up command 4040H, a write command 1010H, etc.
In a memory card with simplified circuitry, the function of the card control section 103 may be limited to only a decode function which uses an address signal. In such a memory card, a bus width of the data bus DBxe2x80x2 between the card control section 103 and the component memory section 102 may be fixed to 16 or 8 bits, and the component memory section 102 and the host system 100 may be directly connected to each other through the data bus DB. In this case, each of the signal lines for the write enable signal WE#, the output enable signal OE#, and the reset signal RESET between the host system 100 and the card control section 103 is directly connected to each of the corresponding signal lines for the write enable signal WE#xe2x80x2, the output enable signal OE#xe2x80x2, and the reset signal RESETxe2x80x2 between the card control section 103 and the component memory section 102 without passing through the card control section 103.
When the component memory section 102 includes a plurality of memories, the card control section 103 has a function of decoding an upper bit portion of an address signal to select a memory with a corresponding address to the address signal.
In a memory card having the above-described conventional configuration, there is a case where the host system 100 checks the device ID output from the memory card 101 and determines that the memory card 101 is not compatible with the host system 100 even though they have compatibility of an algorithm with each other. In this case, operations between the host system 100 and the memory card 101 cannot be performed according to a command signal. As an example of solving such a problem, Japanese Laid-Open publication No. 11-328009 proposes xe2x80x9cA MEMORY CARD AND A METHOD OF DETERMINING OPERATING COMPATIBILITY USING SUCH A MEMORY CARDxe2x80x9d. FIG. 4 illustrates a configuration of such a memory card.
FIG. 4 is a block diagram illustrating a second exemplary configuration of a conventional memory card. In FIG. 4, a memory card 201 includes an address decoder 202, first and second memories 203 and 204, a command decoder 205, a sequencer 206, a register 207, a status register 208, and a table storage section 209.
The address decoder 202 decodes an address signal input through an address bus AB from a host system 200, and outputs a chip enable signal CE# to the first memory 203 or the second memory 204. This allows the first memory 203 or the second memory 204 to be exclusively selected.
The first and second memories 203 and 204 receive a command signal output from the host system 200 through a data bus DB. The memory selected according to the chip enable signal CE# output from the address decoder 202, i.e., the first or second memory 203 or 204, operates according to the command signal input from the host system 200.
The command decoder 205 decodes a command signal input through the data bus DB, and outputs a trigger signal to the sequencer 206 based on the decoded result.
The sequencer 206 is activated by the trigger signal output from the command decoder 205 to control the register 207, the status register 208 and the table storage section 209. The register 207 is connected to the host system 200 through the data bus DB. The register 207 stores a device ID (a manufacturer code and device code) input from the host system 200. The table storage section 209 has a device ID table. The device ID table includes device IDs (a manufacturer code and device code) of IC memories which form the first and second memories 203 and 204 in a tabular format. A memory card including an IC memory which has a device ID identical to the device ID stored in the register 207 has operation compatibility with the host system 200. The sequencer 206 checks whether the device ID stored in the register 207 is included in the device ID table. If so, for example, a xe2x80x9c00hxe2x80x9d code is set in the status register 208, and if not, for example, an xe2x80x9cFFhxe2x80x9d code is set in the status register 208.
The register 207 is connected to the host system 200 through the data bus DB. The device ID (a manufacturer code and device code) input through the data bus DB is temporarily stored in the register 207 according to an instruction from the sequencer 206.
The status register 208 is connected to the host system 200 through the data bus DB. When the host system 200 reads the xe2x80x9c00hxe2x80x9d code from the status register 208, the host system 200 determines that the memory card 201, which includes the IC memories forming the first and second memories 203 and 204, has operation compatibility with the host system 200, and then performs an operation, such as reading, writing, or deleting of data in the memory card 201. When the host system 200 reads the xe2x80x9cFFhxe2x80x9d code from the status register 208, the host system 200 can only read data from the memory card 201.
The table storage section 209 has the device ID table. The device ID table includes device IDs (a manufacturer code and device code) of IC memories which form the first and second memories 203 and 204 in a tabular format. A memory card including an IC memory which has a device ID identical to the device ID stored in the register 207 has operation compatibility with the host system 200.
In the above-described configuration, the device ID table of the table storage section 209 prestores identification information (device IDs) which indicates compatibility of an algorithm with the first and second memories 203 and 204.
When the host system 200 notifies the memory card 201 of device IDs which are compatible with the host system 200, the memory card 201 determines whether or not the notified device IDs exist in the device ID table, and outputs the determination result (which represents presence/absence of such a device ID) to the host system 200.
The host system 200 checks the memory card 201 based on the determination result produced in the memory card 201 instead of the device ID in order to determine whether or not the memory card 201 is compatible with the host system 200. When the device ID table includes no device ID which is identical to any of the device IDs notified by the host system 200, the host system 200 determines that the memory card 201 is not compatible therewith.
In the above-described conventional memory card 101 of FIG. 3, many memories which can be used as the component memory section 102 have compatibility of an algorithm with the host system 100. However, even if such an algorithmically-compatible memory is used as the component memory section 102, when the device ID (a manufacturer code and device code) of the memory is not registered in the host system 100, the host system 100 determines that the memory card 101 including the algorithmically-compatible memory in the component memory section 102 is not compatible with the host system 100. Therefore, due to the determination result, the memory card 101 cannot be used with the host system 100 although the memory card 101 meets the requirements for use with the host system 100 except that the device ID is different.
The memory card 201 of FIG. 4 determines whether or not the device ID table includes a device ID of a memory which is compatible with the host system 200. The determination result is output to the host system 200. In the case where the memory card 201 is used with the host system 200, the host system 200 is required to have software with a function of detecting the determination result produced by the memory card 201. In this configuration, device IDs of memories which are compatible with the host system 200 are preregistered in the device ID table in the memory card 201. This is useful for the memory card 201 to be widely used and have wide application. However, when the host system 200 does not have a detection function as described above, and the host system 200 receives the device IDs of the component memory sections 203 and 204 output from the memory card 201 and determines whether or not the component memory sections 203 and 204 are compatible with the host system 200, the memory card 201 cannot be used with the host system 200. In the case where the host system 200 determines that the memory card 201 is not compatible therewith although the memory card 201 can actually be used with the host system 200, when a user desires to make the memory card 201 compatible with the host system 200, the user is required to update the software of the host system 200 or to modify a device included in the host system 200.
In general, even a memory which is of the newest model becomes an out-of-date product along with the development of the production process. In view of such an alternation of generations, the life span of a memory product is considered to be not more than approximately 10 years. On the other hand, the life span of the host system 200 is generally 10 years or more. Therefore, if the manufacturer stops producing the memories used by the memory card 201, the memory card 201 may not be supplied. In such a case, it is only necessary to make a change in software or hardware of the host system 200 so that a device ID of the component memory section 203 can be recognized by the host system 200. However, it is extremely difficult to make such a change in the software or hardware of a host system which is already on the market.
A memory card connected to a host system according to the present invention includes a command detection section for detecting an identification code (device ID) transmission request command which is input from the host system and an identification code control section for outputting to the host system, in response to a detection signal output from the command detection section, a predetermined identification code which indicates compatibility of the memory card with the host system, and thus an objective of the present invention can be achieved.
In general, a memory card including a memory, which has compatibility of an algorithm with a memory compatible with a host system and does not have an identification code which indicates compatibility of the memory card with the host system, can not be used with the host system. However, in the above-described configuration according to the present invention, the memory card may output an identification code which indicates compatibility of the memory card with the host system other than an identification code (e.g., device ID) preregistered in the memory card (e.g., in a component memory section) in response to an identification code (device ID) transmission request command which is input from the host system to the memory card, so that the memory card can identify itself to the host system as a memory card compatible with the host system. Therefore, the memory card may be used with the host system without changing software or hardware of the host system even if the memory used by the memory card becomes an out-of-date product along with developments in the design and production of the memory.
Moreover, the memory card according to the present invention may further include a component memory section for storing a device ID and an output conversion section for outputting, in response to the detection signal output from the command detection section, an output prohibition signal which prohibits the component memory section from outputting data.
In this configuration of the present invention, by detecting the identification code transmission request command, it is possible to readily switch output operation between the component memory section and the host system to output operation between the identification code control section and the host system. Therefore, when the command detection section detects the identification code transmission request command, an identification code stored in the identification code control section which indicates compatibility of the memory card with the host system may be automatically output to the host system instead of outputting an identification code (e.g., device ID) stored in the component memory section to the host system.
Moreover, the identification code control section in the memory card according to the present invention may include an identification code table for storing the predetermined identification code and an identification code output section for outputting the predetermined identification code stored in the identification code table to the host system.
In this configuration of the present invention, the memory card may prestore identification codes (e.g., device IDs) which indicate compatibility of the memory card with host systems in an identification table so as to selectively obtain an identification code desired by a user from the identification table.
Moreover, the identification code control section in the memory card according to the present invention may include an identification code table for storing a plurality of identification codes, a select circuit for selecting one of the plurality of identification codes stored in the identification code table and an identification code output section for outputting the identification code selected by the select circuit to the host system.
In this configuration of the present invention, the memory card may readily select a desired identification code corresponding to a host system to be used from a plurality of identification codes stored in an identification code table using a select circuit so as to output the selected identification code to the host system.
Moreover, the identification code used for the memory card according to the present invention may include a manufacturer code and a device code.
In this configuration of the present invention, various identification codes (e.g., device IDs), in which each identification code includes a manufacturer code and a device code of a memory, may be preset in an identification table, depending on a host system to be used, during production process, etc.
Thus, the invention described herein makes possible the advantages of providing a memory card which can be determined to be compatible with a host system by the host system without requiring any change in software or hardware of the host system even when the memory card, which has compatibility of an algorithm with a memory compatible with a host system, has a device ID which is different from a preregistered device ID.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.